(a) Field of the Invention
The present invention relates to a semiconductor device having an improved through-hole structure, and in particular, to a semiconductor device having an improved through-hole structure in a multi-layer interconnection structure.
(b)Description of the Related Art
A general construction of a conventional semiconductor device having a multi-layer interconnect structure is shown in FIGS. 1A and 1B, which illustrate a through-hole (via) structure connecting two interconnection layers formed by different steps. FIG. 1A illustrates a first layer interconnects A11, A12 and A13 made of aluminum or aluminum alloy, a second layer interconnects A21, A22 and A23 made of aluminum or aluminum alloy, which correspond to the respective underlying first layer interconnects A11, A12 and A13, and through-holes T11, T12 and T13 which connect corresponding interconnects together in both the layers. In the region where the overlying second layer interconnect A23, for example, and the underlying first layer interconnect A13 are connected together by the through-hole T13, margins "d" and "a" are required of the through-hole T13 on a mask pattern with respect to both the second layer interconnect A23 and the first layer interconnect A13. These margins are provided to prevent the through-hole T13 from offsetting or protruding outside the first and second layer interconnects A13 and A23 due to an error or variation in a photolithographic etching process.
FIGS. 2A and 2B show a top plan view of the contact regions of FIG. 1A and a cross sectional view taken along line X-X' in FIG. 2A, respectively. In the fabrication step of the conventional device, an insulating laminate B1 including a plurality of oxide films is formed by iterative depositing steps on a silicon substrate Jk. First layer interconnects A11, A12 and A13 and second layer interconnects A21, A22 and A23 are formed between the depositions of the oxide films and disposed in correspondence to the through-holes T11, T12 and T13, respectively. It will be noted that the first layer interconnect A13, for example, is coupled to the overlying second layer interconnect A23 with the margin "a" with respect to the location of the through-hole T13 at both edges of the interconnect A13. In this respect, there is also disposed the margin "d" for the overlying second layer interconnect A23 with respect to the location of the through-hole T13.
In FIG. 2A, the space or gap between the adjacent two of the first layer interconnects A11, A12 and A13 is denoted by "b" and the space between the adjacent two of the second layer interconnects A21, A22 and A23 is denoted by "n". A first total width "W", which represents the total width necessary for arranging the first layer interconnects A11, A12 and A13, is expressed as follows: EQU W=3.times.(2a+i)+2b=6a+3i+2b,
wherein "i" represents the width of each through-hole.
A second total width Wa2, which represents the total width necessary for arranging the second layer interconnects A21, A22 and A23, is similarly expressed as follows: EQU Wa2=3.times.(2d+i)+2n=6d+3i+2n.
FIGS. 3A and 3B shows, similarly to FIGS. 2A and 2B, another interconnect structure having buried contacts. The illustrated structure is different from the structure of FIGS. 2A and 2B in that overlying second layer interconnects (not shown) is formed after the deposition of the buried through-holes A11, A12 and A13. In this structure, the total width of the space for arranging the interconnects A21, A22 and A23 are 6a+3i+2b, which is substantially same as the semiconductor device of FIGS. 2A and 2B.
In order to reduce the space for disposing the interconnects, an arrangement shown in FIG. 1B may be employed in place of FIG. 1A in consideration of the above facts. Specifically, in FIG. 1B, three through-holes T11, T12 and T13 similar to those shown in FIG. 1A are disposed so that each adjacent two of the through-holes are offset from each other in the longitudinal direction of the interconnects for reduction of the total width of the interconnects By this configuration, it is possible to reduce the total width "W" shown in FIG. 1A by the margin "a" to obtain a reduced width which is equal to "W-a". However, in this configuration, the longitudinal length "V" of the first layer interconnects A11, A12 and A13 is increased by .beta. at the location of the through-holes T11, T12 and T13 to thereby result in the length "V+.beta." of the space for disposing the through-holes T11, T12 and T13, as shown in FIG. 1B. As a consequence, while the total width "W" can be reduced in the transverse direction, the length "V" increases in the longitudinal direction of the interconnects.
Further, if the pattern illustrated in FIG. 1B is repeated for a large number of the interconnects, the increase of the longitudinal length by .beta. has a more significant effect upon the area of the mask pattern. A repetition of such an identical pattern is notable in a semiconductor chip having memory cells, for example, and especially in the memory cell array area and in the peripheral circuit area disposed in the vicinity of the memory cell array area. It will be noted that the peripheral circuit area is directly connected with memory cells, and accordingly, a large number of peripheral circuit areas equal in number to the columns or rows of the memory cells are located adjacent to the memory cell array area.
FIG. 4 is a schematic top plan view of a conventional semiconductor memory device. A peripheral circuit area AR is disposed for peripheral circuit blocks, which are disposed at the same pitch as the row or column of the memory cells in the memory cell array area. The peripheral circuit area AR for a 1-megabit memory device, for example, includes a column circuit area RK having digit lines and sense amplifiers and a row circuit area KK having word lines and row decoders, each circuit area including 256 to 2048 circuit blocks or more in number. If the total width "W" which is equal to 6a+3i+2b for the first layer interconnects in FIG. 1A is applied to the column circuit blocks in FIG. 4, it will be noted that the width CW required for disposing the column circuit blocks will amount to approximately W.times.(256 to 2048), which significantly increases the chip size of the memory device.
If the arrangement illustrated in FIG. 1B is applied to the memory device of FIG. 4 for reduction of the required chip size CW by an amount corresponding to a.times.(256 to 2048), there results an increase in the area corresponding to .beta..times.L.times.2, wherein L is the length of the side of the chip. In other words, it may be concluded that a reduction in the chip size of the semiconductor memory device is not achieved.
The same applies to the case where the arrangement shown in FIG. 1A is used for the row circuit blocks. The required size CW' is approximately equal to W.times.(256 to 2048). If the arrangement shown in FIG. 1B is employed, although a reduction by an amount corresponding to a.times.(256 to 2048) is possible, an increase in the chip area results, which corresponds to .beta..times.L.times.2. It is to be noted that since the peripheral circuit area AR contains a mask pattern having a very small size, the desired circuit can be obtained substantially solely by a multilayer interconnection structure and corresponding through-holes. That is, the number of through-holes is significantly larger in the peripheral circuit area than in the memory cell array area. Currently, the contact areas occupy on the order of about 30% of the peripheral circuit area AR, and this represents one of the factors which increase the occupied area of the semiconductor memory device.
FIGS. 5A and 5B show cross sections of semiconductor devices described in Patent Publications JP-A-4(1992)-93048 and JP-A-3(1991)-231429, respectively, each having a multi-layer interconnection structure. In these semiconductor devices, a conductive material "D" such as tungsten is used in through-holes JT1 for connecting multilayer interconnects including silicon substrate Ja1, a first layer interconnect Ja2, a second layer interconnect Ja3, and a third layer interconnect Ja4, the through-holes being formed by a single photolithographic etching step using a common glass mask. FIG. 5A shows that interconnects in the respective layers Ja1 to Ja4 are collectively connected together by the through-holes, and FIG. 5B shows that interconnects in various layers except for the silicon substrate Ja1 are collectively connected together by the through-holes.
When these techniques are employed to define through-holes in a semiconductor device having a multi-layer interconnection structure, an advantage is attained that the number of steps, manpower and costs can be reduced by using a single glass mask for patterning the through-holes, in contrast to a large number of glass masks for patterning an interconnection structure in the conventional semiconductor device, especially when the design for the semiconductor device is changed or improved.
It will be noted that the margin required for the through-holes JT1 connecting the first layer interconnects Ja2 and the second layer interconnects Ja3 is similar to that illustrated in FIGS. 1A, 1B and 2, which means that reduction of the semiconductor chip size is not attained by these techniques.
Patent Publication No. JP-A-6(1994)-350055 describes a through-hole structure for reducing the number of steps, as shown in FIG. 6. The described technique is applied to memory cells in a SRAM having a high-resistance load resistor. Specifically, a drain electrode Jb2 of a first driver transistor, a gate electrode Jb3 of a second driver transistor, and a terminal of high-resistance load resistor Jb4 are collectively connected to a through-hole Jb7, which is provided for the contact for the drain Jb2 of the first driver transistor. This structure allows a single etching step to form the contact between a plurality of layers, thereby reducing the number of fabrication steps, period and the costs. However, this technique only applies to a SRAM memory cell having a high-resistance load resistor. Besides, while this technique is applied to a multi-layer interconnection structure, a margin is required of the contact Jb7 relative to the N+drain electrode Jb2, or first layer interconnect, and hence a reduced pattern area cannot be obtained. In addition, since the through-hole Jb5 is connected to the drain electrode Jb2, there results a forward-biased current flowing from P-type substrate Jb1 through the drain electrode Jb2 to the aluminum interconnect Jb6 if a potential below the potential of the P-type substrate Jb1 occurs on the aluminum interconnect Jb6. Moreover, since the drain electrode Jb2 involves a parasitic capacitance significantly greater than the capacitance of the interconnects, a high speed operation cannot be obtained in the memory device.
While the techniques in the prior art have been discussed above, any of them requires a margin for the through-hole to assure the electric contact between the overlying layer interconnects and the underlying layer interconnects, although these techniques achieve a reduction in number of steps or prevention of a penetration failure involved in the through-hole. That is, these techniques do not achieve a reduction of masked area in the semiconductor device without reduction of the contact area between interconnect layers.